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Joint Processing Platform

Coordination: KTH

Contact person: Per-Erik Hellström,


The Joint Processing Platform is established to allow access to the processing resources and competence within the Sinano Institute members.

The platform is based on MOSFET device fabrication on 100 mm Si or SOI wafers although several process steps can be performed on small pieces and up to 200 mm wafer size. A major objective is to evaluate and integrate new materials/process modules in MOSFETs.

The processing competence among the partners is used to tune the MOSFET process flow for flexible integration of new materials/process modules to allow evaluation on fully processed devices. The turn-around-time for standard MOSFET fabrication is 3,5 month and gate lengths/fin widths down to a few tens of nm are available.

The Joint Processing Platform also assists partners to get access and know-how of specific processes not available at the home institution in the field of other advanced More Moore, More than Moore and Beyond-CMOS devices


If you want to send a Request Form, Please, CLICK HERE