Sinano Workshop 2007

The third Sinano Workshop took place during the ESSDERC-ESSCIRC Conference in Munich, Germany on September 14th, 2007

Programm of the workshop

“Carrier Mobility enhancement in strained Silicon Germanium channels ” – D.R. Leadley, A. Dobbie, G. Nicholas, M. Merius (Warwick University, IMEC) 

“Metallic Source/Drain architecture: status and prospects ” – E. Dubois, G. Larrieu, N. Breil, M. Ostling, P.E. Hellström, N. Reckinger, X. Tang, S. Mantl (IEMN, STMicroelectronics, KTH, UCL, FZ-IBN1-Julich)

“Novel High k/Metal gate materials ” – O. Engstrom, P.K.Hurley, O. Buiu, M.C.Lemme (Chalmers Univ., Tyndall, Liverpool Univ., AMO GmbH) 

“SON Nanodevices ” – T. Skotnicki (STMicroelectronics)

“Multisubband Monte Carlo simulations for holes ” – D. Esseni (Univ. Udine) 

“Multi-gate and Muti-wire Nanodevices ” – T. Poiroux, T. Ernst (CEA-LETI)

“Understanding quasi ballistic transport in Si and alternative channel materials ” – R. Clerc, P. Palestri (IMEP-FMNT, Univ. Udine) 

“Growth of Carbon Nanotubes with CMOS compatible catalysts ” – P. Ashburn (Southampton Univ.) 

“Si and Ge Nanowires: challenges and prospects ” – J.P. Raskin, M. Lemme, E. Dubois, A. Ionescu, T. Baron, P. Gentile (UCL, AMO GmbH, IEMN, EPFL, LTM-FMNT, CEA) 

“1D BTE for Nanowires ” – S. Reggiani (ARCES)

“Graphene devices ” – M. Lemme (AMO GmbH) 

“Performance Challenges of Future DRAMs ” – J. Faul (Qimonda)