Platforms

Characterization Platform

Coordination: Grenoble INP

Contact person: Gérard Ghibaudo, ghibaudo@minatec.inpg.fr

The Joint Characterization Platform has been established to allow access to the characterization facilities to all NANOSIL partners. Access can be made available to external organization.

Example of facilities concern:

Electrical characterization

  • LF electrical characterization (admittance, CV, IV, 1/f noise) of silicon based materials and devices
  • Room to low temperature magneto-transport in high magnetic fields (Hall, mobility…°)RF a
  • nd HF characterization at wafer level up to 110 GHz and down to 30K (S parameters, noise, power)
  • Transient and fast current measurements, Setup for measurements of ring oscillators
  • EEPROM memory programming/erasing/retention  characterizationDefects and interface quality characterization by C-V, G-w, charge pumping, DLTS, TSC, transient analysis…
  • Reliability characterization (breakdown, hot carrier stress, BTI, BTS…)
  • Sub-nm depth profiling for doping/mobility data in Si and strained Si

Optical characterization

  • Absorption measurements, wavelength range UV-VIS-IR
  • Photoluminescence (PL) and micro spot Photoluminescence (µPL)
  • Laser excitation: 325 nm, 457.8nm, 488nm, 514.5nm
  • Spectrometer: 350nm-1600nm
  • Electroluminescence (EL): 350nm-1600nm
  • Photocurrent-photovoltage (UV-VIS)

Physical and structural characterization

  • Physical characterization of silicon based materials by SIMS, XRD, HRTEM, AFM, HRSEM, ellipsometry, FIB, RBS, channeling, MEIS, ESCA, XRR…
  •   Near field microscopy by AFM (STM, SGM, TUNA, EFM, MFM…)
  •  Sub-nm depth profiling of strain and composition (Si, SiGe)
  • Nanoscale strain measurements using TERS with complementary finite element modeling
  • Micro-Raman: Composition and stress determination Simultaneous evaluation of surface roughness, strain and related defects
  • Real-time monitoring of strain/morphology evolution on a nanoscale during thermal processing
  • Defect identification: misfit dislocations, stacking faults and threading dislocations
  • Surface analysis, Line Width Roughness ans critical dimension metrology on patterned surfaces by 3D AFM
  • MEMSNEMS characterization (vibration, sensitivity, mechanical, thermal…)

The Joint Characterization Platform also assists partners to get access and know-how of specific processes not available at the home institution.

If you want to send a Request Form, Please, CLICK HERE

Processing Platform

Coordination: KBH

Contact person: Per-Erik Hellström, pereh@kth.se

 

The Joint Processing Platform is established to allow access to the processing resources and competence within the Sinano Institute members.

The platform is based on MOSFET device fabrication on 100 mm Si or SOI wafers although several process steps can be performed on small pieces and up to 200 mm wafer size. A major objective is to evaluate and integrate new materials/process modules in MOSFETs.

The processing competence among the partners is used to tune the MOSFET process flow for flexible integration of new materials/process modules to allow evaluation on fully processed devices. The turn-around-time for standard MOSFET fabrication is 3,5 month and gate lengths/fin widths down to a few tens of nm are available.

The Joint Processing Platform also assists partners to get access and know-how of specific processes not available at the home institution in the field of other advanced More Moore, More than Moore and Beyond-CMOS devices

If you want to send a Request Form, Please, CLICK HERE

Modelling Platform

Coordination: IUNET

Contact person: Enrico Sangiorgi, esangiorgi@arces.unibo.it

The Joint Modelling Platform has been established to continue and further develop the positive experience of the SINANO NoE by integrating and validating the modelling approaches and tools developed by the individual partners against ad-hoc, well-characterized template devices.

The most promising and advances modelling tools-methods are brought together to tackle the main device physical challenges foreseen for the 22, 16 TN and beyond …(mobility enhancements, off currents, interface effects, low dimensional transport).

Methods and Tools for Device modelling

  • Semi-classical device modeling (Boltzmann equation):
  • Quantum Drift-Diffusion
  •  Multi-Sub-Band Monte Carlo
  • Deterministic solutions of the Boltzmann Equation
  • Approaches for different carrier gas dimensionality, corresponding to planar bulk and MUG-MOS (2D) or nanowire FET (1D).
  • Full-quantum device modeling
  • Non Equilibrium Green Functions (NEGF)
  • Wigner-Boltzmann
  • Gate leakage modelling, including high-k materials and trapping
  • Modeling of intrinsic device parameters variability
  • Calculation of  the sub-band structure for the 2D, 1D, electron and hole carrier gases and of the corresponding scattering rates
  • Effective mass approaches
  • k.p approaches

Methods and Tools for Compact modelling

  • Compact models for thin body multi-gate MOSFETs and for FinFETs including size induced quantization and quasi-ballistic transport
  • Compact models for MASTAR environment
  • Compact models to account for the main sources of intrinsic statistical variability

The Joint Modelling Platform also assists partners to get access and know-how of specific processes not available at the home institution.

If you want to send a Request Form, Please, CLICK HERE