Sinano Workshop 2005

The 1st Sinano Workshop was held just after the ESSDERC-ESSCIRC conference in Grenoble, on September 16th, 2005.

Programm of the Workshop

Ken Uchida, Toshiba, “Transport in ultra-thin SOI devices 

Luca Selmi, Univ. Udine, “Modeling approaches for Decananometer MOSFETs within SINANO 

A. O’Neill, Newcastle Univ., P-E. Helstroem, M. Ostling, KTH, K. Lyutovich, E. Kasper, Stuttgart Univ., “Advancing Strained Silicon 

Siegfried Mantl, Forschungszentrum Juelich, “Novel Virtual Substrates for Strained SOI 

Jean-Pierre Raskin, UCL, Abhisek Dixit, Nadine Collaert, IMEC, Tamara Rudenko, ISP Kiev, Tsung Ming Chung, Denis Flandre, Valeria Kilchytska, Dimitri Lederer, UCL, “FinFET: a mature multi-gate MOS technology ? A wideband transistor simulation and characterization approach 

J. Knoch, Forschungszentrum Juelich, E. Dubois, G. Larrieu, IEMN, N. Reckinger, X. Tang, V. Bayot, UCL, “Recent advances in metallic source/drain engineering 

Yoshio Nishi, Stanford University, “Current Status and Trends of Nanoelectronic Devices 

Jimmy Xu, Brown University, “Molecular/carbon nanotube electronics 

A. Ionescu, EPFL, ”Hybrid CMOS-Nanowire circuit architectures for digital and analog applications 

M. Sterkel, T. Nirschl, M. Fulde, P.-F. Wang, D. Schmitt-Landsiede and W. Hansch, Technical Univ. Munich, “Complementary Tunneling-Transistors (TFET): Fabrication and Application down to the 65nm CMOS-node 

Philippe Dollfus, IEF, “Post-CMOS generation: the different modeling approaches developed within SINANO for nanotubes, nanodots and resonant tunneling devices